(Singapore)
Product Summary
The MT48LC32M8A2P-75IT is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quadbank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). The MT48LC32M8A2P-75IT is organized as 8,192 rows by 1,024 columns by 8 bits. The MT48LC32M8A2P-75IT is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible.
Parametrics
MT48LC32M8A2P-75IT absolute maximum ratings: (1)Voltage on VDD, VDDQ Supply Relative to VSS: -1V to +4.6V; (2)Voltage on Inputs, NC or I/O Pins Relative to VSS: -1V to +4.6V; (3)Operating Temperature, TA (commercial): 0℃ to +70℃; (4)Operating Temperature, TA (industrial IT): -40℃ to +85℃; (5)Storage Temperature (plastic): -55℃ to +150℃; (6)Power Dissipation: 1W.
Features
MT48LC32M8A2P-75IT features: (1)PC66-, PC100-, and PC133-compliant; (2)Fully synchronous; all signals registered on positive edge of system clock; (3)Internal pipelined operation; column address can be changed every clock cycle; (4)Internal banks for hiding row access/precharge; (5)Programmable burst lengths: 1, 2, 4, 8, or full page; (6)Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes; (7)Self Refresh Mode; (8)64ms, 8,192-cycle refresh; (9)LVTTL-compatible inputs and outputs; (10)Single +3.3V ± 0.3V power supply.
Diagrams
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